To design, layout and simulate 4 bit synchronous ALU to store the final output in a register using CMOS technology in MIT/LL 250nm Low power SOI CMOS technology [Virtuoso Cadence]
Project Material
Results & Conclusion
Transistor sizing, Schematic design, timing analysis using Spectre, generating netlists, layout design, DRC/LVS, optimize the layout area and propagation delay, simulation with and without layout parasitic's.
Designed the layout with minimum area and least propagation delay keeping in mind of all the technological constraints
ALU performed the following operations: addition, addtraction, 1's and 2's complement, bitwise Nand and Nor operation
Team Info
Akhil Mulpuri
Ila Tatke
Harsha Akkipedi
Contact
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