The key problems in designing of VLSI circuits are high power consumption, larger area utilization and delay which affect the speed of the computation and also results in power dissipation. In general speed and power are the essential factors in VLSI design. For solving the issues, a new architecture has been proposed. In the proposed system, the two high speed multipliers, Modified booth multiplier (MBM) and the Wallace tree multiplier are hybridized with Carry Look Ahead adder (CLA) and formed a hybridized multiplier which delivers high speed computation with low power consumption.
MBM is proposed to reduce the partial products whereas Wallace tree multiplier is accompanied for fast addition and CLA is used for final accumulation. This hybrid multiplier produces better results in terms of speed and power than the conventional designs. The simulation results prove that the hybrid architecture is superior to other multipliers.
Project Material
Results & Conclusion
The Hybrid multiplier has been coded using Verilog Hardware Description language using Xilinx Software Package.
Designed a Hybrid multiplier combining both the Booth and Wallace Tree multipliers and partly implement it in FPGA.
Project lead and programmed the entire project in Verilog HDL in Xilinx ISE Tool.
The resulting time efficiency is 40% more than the array multiplier and 10% more than Wallace Tree multiplier for 8 bit inputs.
Team Info
Sai Siva Prasad
Srinivas
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