The main motto of this project was to familiarize ourselves with the combination and the sequential deisgn.
The first half of the project was to design a 16 bit adder using schematic using Divide & Conquer approach using different strategies to minimize the delay, hardware cost and power.
The second half was to design a Moore action FSM controlled add-and-shift Booth multiplication using One hot style. This project as a whole was a good experience as we designed an FSM, Datapath and controlled the datapath using the FSM keeping in mind all the timing constraints, which play a vital role in sequential design.
Results & Conclusion
Designed, simulated, verified the 16 bit 3 number adder that produces 18 bits output using divide and conquer approach by resolving the dependencies using wait and Design for all Cases (DAC) strategies and generalized the design for n bit adder.
The design using DAC was 15% faster than wait strategy at the expense of additional hardware cost.
Designed, performed functional simulation,timing simulation and static timing analysis(STA) of Moore action FSM controlled add-and-shift Booth's multiplication in One-hot designstyle.
Designed it for a lowest clock period with correct simulated outputs and keeping the quality of timing metrics in mind.
Team Info
Aditya Chaudhary
Contact
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